IWR6843AOP · PROC091G Rev G · SWRR197

Hardware Bring-up Lab

Schematic review checklist, DC power rail verification, and T1–T6 test sequence for the IWR6843AOP EVM Rev G bring-up. Based on TI SWRR197.
Completion0%
Schematic items0/32
Sub-tests passed0/21
T-stages passedT0/6
T1–T6 Bring-Up Test Sequence · Click stage to cycle status · Expand for sub-tests
T1
Blank Board
Pre-Assembly
Pending
T2
Assembled
Post-Assembly
Pending
T3
Power Up
Power-On
Pending
T4
Digital IO
Peripherals
Pending
T5
RF Tests
RF
Pending
T6
System
End-to-End
Pending
§ 01

Schematic Review

SWRR197 SCH_Checklist — all sections must be signed off before fab order
Reference Clock
0/4
nRESET & Error Signals
0/4
SOP Boot Mode Pins
0/4
QSPI Flash
0/4
Host SPI (Secondary)
0/4
UART / Control Port
0/3
JTAG Debug
0/3
I2C
0/2
Miscellaneous
0/4
0/4
Reference ClockPin A7, B7, A14
▲
40 MHz XTAL connected between CLKP (A7) and CLKM (B7)
4.7 pF load caps on both CLKP and CLKM
Low-capacitance guard ring routing — keep CLKP/CLKM short
⚠ High-risk trace; avoid vias; route away from switching supplies
OSC_CLK_OUT test point placed (A14, K3) for APLL frequency verification
0/4
nRESET & Error SignalsPin U11, U13–U15
▼
0/4
SOP Boot Mode PinsPin U10, M3, V10
▼
0/4
QSPI FlashPin H3, G2, J3, K2, H2, J2
▼
0/4
Host SPI (Secondary)Pin C2, D2, D1, F2
▼
0/3
UART / Control PortPin U16, V16, E2, D3
▼
0/3
JTAG DebugPin T3, U9, U10, TMS
▼
0/2
I2CPin G3, G1
▼
0/4
MiscellaneousPin V2, M2, P17–T18
▼
§ 02

DC Power & PMIC

LP87524J reference — 5V input, 4 regulated outputs + ext RF LDOs
RailNominalLoad / FunctionSource
VDD121.2 VDigital corePMIC BUCK1 (LP87524J)
VDDR1.0 VInternal cache / DDRPMIC BUCK2
VIOIN1.8 VI/O ring, pullup supplyPMIC BUCK3
VIN_RF11.3 VRF LDO 1PMIC BUCK4 / ext LDO
VIN_RF21.3 VRF LDO 2PMIC BUCK4 / ext LDO
VDD333.3 VAnalog / peripheral supplyPMIC input or external
VBGAP~0.9 VInternal bandgap ref (probe only)Internal — do not drive
§ 03

SOP Boot Modes

Sense-on-Power — pins latched at nRESET 0→1; never change at runtime
001
Functional / Flash-Boot
Normal steady-state operation. Boots firmware from QSPI flash. MSS Logger output active.
010
Flash Programming
UART download mode. AM62 asserts UART break → streams metaImage via UniFlash or mmWave SDK flash tool on Control UART.
flash command
# SOP[2:1:0] = 010, UART break, then stream
python3 mmwave-sdk/tools/flash/UniFlash.py \
  --port /dev/tty.usbserial-XXXXX \
  --image metaImage.bin
100
Debug / Development
JTAG + CCS attach mode. Used during IWR6843AOP firmware development with XDS110 probe.
§ 04

Resources

Design files, datasheets, and tools — all in ambientintel/ambient-device-fw
Datasheet
IWR6843AOP Datasheet (TI)
docs/datasheets/iwr6843aop.pdf
Datasheet
IWR6843AOP v1.1 (Mistral)
docs/datasheets/IWR6843AOPv1_1.pdf
Datasheet
60 GHz Industrial AoP Radar
docs/datasheets/60GHz-Industrial-AoP-Radar.pdf
Altium
EVM Design Package Rev G (sprr418)
docs/sprr418/Rev.G/
BOM+Sch
Assembly Package Rev G ES2 (swrr166)
docs/swrr166/ES2 (Rev. G)/
Checklist
SWRR197 HW Bring-up Checklist
docs/xWR6843AOP_HW_BringUp_Schematic_and_Layout_Checklist.xlsx
App Note
Bootloader Flow SWRA627
ti.com/lit/an/swra627/swra627.pdf
SDK
mmWave SDK v03.06.02.00-LTS
Current SDK for IWR6843AOP — TI Resource Explorer